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ASIC Fundamentals: The Architect

Looking to the current ASIC design projects, we see a discrepancy. The EDA companies push a narrative that all is well as long as you buy their tool chain. That is what I call the Disney version of reality. Real projects today rarely start with a signed off specification. Modeling the chip for feasibility is rare today. Without the proper validation and spec...

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ASIC fundamentals: The clock reset module

The architect of the chip needs to foresee the future. Therefor, it is important to understand the clock and reset network. Big synchronous clock domains get in trouble during the back-end clock tree synthesis. Avoiding problems like that is the value of the architect. Based on the requirements, the architect writes a specification and draws a top-level bloc...

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ASIC FUNDAMENTALS: how do ASIC clocks fit into an FPGA?

One of the major differences between software and hardware is the concept of a clock. It defines the rhythm the sequential elements update inside the chip. Note that in complex System-On-Chips (SoC) there are many clock frequencies that distribute to parts of the silicon. In this post, we will take a basic look at a clock. At the bottom of this post, you wil...

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ASIC FUNDAMENTALS: how does the back-end engineer deal with clocks?

One of the major differences between software and hardware is the concept of a clock. It defines the rhythm the sequential elements update inside the chip. Note that in complex System-On-Chips (SoC) there are many clock frequencies that distribute to parts of the silicon. In this post, we will take a basic look at a clock. At the bottom of this post, you w...

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ASIC FUNDAMENTALS: how do synthesis and STA deal with a clock?

One of the major differences between software and hardware is the concept of a clock. It defines the rhythm the sequential elements update inside the chip. Note that in complex System-On-Chips (SoC) there are many clock frequencies that distribute to parts of the silicon. In this post, we will take a basic look at a clock. At the bottom of this post, you w...

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ASIC FUNDAMENTALS: how do we deal with multiple clocks?

One of the major differences between software and hardware is the concept of a clock . It defines the rhythm the sequential elements update inside the chip. Note that in complex System-On-Chips (SoC) there are many clock frequencies that distribute to parts of the silicon. In this post, we will take a basic look at a clock. At the bottom of this post, you w...

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ASIC FUNDAMENTALS: do we use an internal or external clock?

One of the major differences between software and hardware is the concept of a clock . It defines the rhythm the sequential elements update inside the chip. Note that in complex System-On-Chips (SoC) there are many clock frequencies that distribute to parts of the silicon. In this post, we will take a basic look at a clock. At the bottom of this post, you w...

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ASIC FUNDAMENTALS: what are the important parameters of a clock?

One of the major differences between software and hardware is the concept of a clock . It defines the rhythm the sequential elements update inside the chip. Note that in complex System-On-Chips (SoC) there are many clock frequencies that distribute to parts of the silicon. In this post, we will take a basic look at a clock. At the bottom of this post, you w...

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ASIC FUNDAMENTALS: what is a clock?

One of the major differences between software and hardware is the concept of a clock. It defines the rhythm the sequential elements update inside the chip. Note that in complex System-On-Chips (SoC) there are many clock frequencies that distribute to parts of the silicon. In this post, we will take a basic look at a clock. At the bottom of this post, you wil...

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ASIC FUNDAMENTALS: how do we design an ASIC?

One of the major differences between software and hardware is the concept of a clock. It defines the rhythm the sequential elements update inside the chip. In complex System-On-Chips (SoC) there are many clock frequencies that distribute to parts of the silicon. And since it is a basic thing for any digital design, let’s look at the ASIC first. So, let’s d...

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What drives the main cost of an ASIC?

The main cost of an ASIC, an Application Specific IC is related to the complexity. Basically, the silicon we start with is a clean slate. Imagine a circular surface, called a wafer, with billions of transistors. With a special technique, we will interconnect all transistors via metal layers on top of the silicon. Then the wafer is cut in squares, called dies...

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ASIC FUNDAMENTALS: what is synchronous design?

One of the major differences between software and hardware is the concept of a clock. In essence, it defines the rhythm of updating the sequential elements in the chip. And we call it synchronous design. In big complex system-on-chips there are many different clock frequencies that are distributed to parts of the Integrated circuit (IC). And digital design...

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Lean Mean Verification Machine: Appetite For Destruction (*)

We all have this inner urge to destroy, isn’t it? Not by default. We are good people, right? It definitely needs a trigger. Some alcohol could do the trick. Or after a bad night of sleep combined with some major setback. Or Saturn lines up with the moon while Venus plays online chess with Mars. This primal instinct is important for the verification engineer....

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Careers in VLSI: who gets the best salary?

Analog, mixed-signal or digital design engineer? None of them get paid what they are worth. Let’s be clear about that. And this is good nor bad, it is the way it is. The stoic does not attach an opinion to an observation. Furthermore the skills for hardware engineers are quite specific and hard to find. Especially if we compare ourselves versus our nemesis...

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Which field of dVLSI has more demand: RTL or verification?

Let’s quickly go through the terminology here: ASIC and FPGA An ASIC is an "Application Specific IC", a chip specifically designed for a specific purpose. An FPGA is a "Field Programmable Gate Array". In essence, it is an ASIC but extra wiring and logic allows you to reconfigure the FPGA to contain a digital circuit over and over again. Both types of chips n...

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dVLSI career: should I go for front-end or back-end positions in ASIC design?

(*) dVLSI is short for digital VLSI. First, let's assume the old school "career" is still a thing for the coming decade. Second, let's assume you are not defining growth as the vertical rise in a big company. Before you say anything, becoming a manager, director and VP is commendable. Because, shit always runs downhill, it is smart to be on the top of the hi...

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What is the job content of a junior (fresh graduate) digital VLSI design engineer?

The three musketeers were actually four, did you know that? D'Artagnan, Athos, Aramis, and Porthos. Yeah, I googled that. Busted. Soit. Like the three musketeers, HDL code comes in two forms most designers can come up with. There is a third form, but let’s not get ahead of ourselves. The FIRST Now, a recently graduated engineer will not touch any RTL design ...

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Xilinx dVLSI remote FPGA design

There is no technical reason to be physically present for 100% of the time for FPGA work. (I am not affiliated with any brand mentioned below) As a poor lonesome dVLSI engineer, I wanted to control my dev boards from a distance. Hence, I hooked up a Raspberry Pi and a cheap RF transmitter to be able to send out click on/off commands. I still use it today, th...

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What are your best ASIC Verification interview questions?

ASIC verification is about verifying the design under test. Hence the experience should not really cover, design, synthesis, STA, DFT, just when it touches verification . You can ask questions related to this but that would be extra experience, a verification engineer verifies. To find out if a verification engineer is junior or senior, you let him or her ta...

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What programming languages does the VLSI industry use?

Programming or not? I don’t like the word programming languages. Even though digital VLSI designers cod in an HDL (verilog, VHDL, systemverilog), it is hardware that they implement, not software. It looks software but in fact it isn’t. There are limitations on the operators and constructs that a synthesis tool can infer from a HDL file. Thus a digital HW des...

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