ASIC FUNDAMENTALS: what is synchronous design?

One of the major differences between software and hardware is the concept of a clock. In essence, it defines the rhythm of updating the sequential elements in the chip. And we call it synchronous design. In big complex system-on-chips there are many different clock frequencies that are distributed to parts of the Integrated circuit (IC). And digital designs come in two main flavors, Application Specific IC (ASIC) and FPGA (Field Programmable Gate Array). We will first look at the ASIC clock specifics and come back to the FPGA clock in another post.

Why synchronous design?

Synchronous design is the cornerstone of abstracting complexity. Because, drawing schematics and logic circuits by hand is not feasible anymore. There are billions of transistors in today's cutting edge System-On-Chips SoC. Therefor EDA tools make the life of the digital designer easier. By writing a description of the hardware, we abstract the logic into a syntax that looks like a normal software language. This description is written in a Hardware description language (HDL). The most known are VHDL and SystemVerilog. Verilog has evolved into SystemVerilog, so for clarity, I refer to SystemVerilog and VHDL as the two most known languages. Second point is that we can automate verification, any time we change the HDL we can regress the verification with self-checking test code. As a result, the tools do the heavy lifting.
Unfortunately, tools have limits. Hence, my life motto, Keep It Simple And Stupid (KISS) applies here. The clock defines the rythm a logic circuit updates its sequential elements (aka flipflops). The path between two such elements is asynchronous or combinational (combinatorial) logic. That means the delay through the logic gates depends on the cloud of logic cells it travels through. By constraining the combinatorial path between two sequential elements, we can simplify the timing analysis of the whole circuit. The delay through the path must be constrained by the clock period. On top of that, our DFT scan chain methodology relies on those sequential elements. DFT patterns are shifted in and out of those chains of flipflops and verify that there are no defects in the manufactured cells on our actual silicon. As a result, we design digital circuits in a synchronous way. Still as an exception to the rule, we can design some time critical paths asynchronously. That means without clock constraint, just the delay through the combinatorial logic.
Now, we have the background information. Synchronous design is intended to simplify and automate. In contrast, schematic entry would produce smaller and more efficient designs. But the cost in man years would be so uneconomic that there is no business case to design the circuit by hand for a "billion-transistor" chip.

In the next post we are going to answer the question: how to design an ASIC?

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