Looking to the current ASIC design projects, we see a discrepancy. The EDA companies push a narrative that all is well as long as you buy their tool chain. That is what I call the Disney version of reality. Real projects today rarely start with a signed off specification. Modeling the chip for feasibility is rare today. Without the proper validation and specification of the idea, the team starts the design. No time to waste, as Greenpeace would say. It reminds me of the fable of the rabbit and the turtle. With the right preparation, one appears to be slow as a turtle in the beginning. But it saves a lot of time and resources once the design phase starts.
“What use are glasses or light if the owl does not want to see?” Corporations hire quality managers, ISO certification externals, because it is hard to enforce a good workflow. Lip service, do as I say, not do as I do.
The twin brother of the specification is the chip architecture. A long-lost art of partitioning a chip in sensible sub-modules. More important today, where power efficiency and power domains are almost standard. Crossing power domains requires level shifters and isolation, so the number of wires crossing a power boundary is important. And the location of the IO pads is important too. The architect must have a rough idea of a floor plan even before the project starts. That is the back-end job that starts only after the whole front-end design cycle delivers a nearly complete technology specific design to the layout engineers. The specification and the architecture of the chip are both a critical but often neglected part of the project.
Clocks and resets
Another crucial item is the clock and reset network in the chip. Sometimes clocks come from the external world, usually a crystal on the PCB. The crystal output connects to an input of the chip. Sometimes, a serial communication protocol like a UART uses that clock locally. Or this clock is the reference clock for a “Phase-Locked Loop” (PLL). A PLL multiplies a reference clock frequency on-chip, usually with non-integer multiples. So, the architect chooses the clock and reset strategy. Again, this person predicts the future. A big chip with one clock domain (synchronous) is impossible in today’s tech nodes. On chip variation and clock skew need compensation with a lot of clock buffers. The back-end engineers that need to do the “clock tree synthesis” (CTS) are not magicians. To reduce the clock buffering, one needs to make parts of the chip synchronous, but their interaction asynchronous. Even if they are all running the same clock frequency, they must keep the clock trees small. That is the added value of a veteran chip architect. Avoiding the problems upfront. Making an extremely performing design that meets the area and power requirements. They are true all-in-one know it all people. True unicorns. Worth their weight in bitcoin, kidding, gold of course.
I have written a series about clocks on my blog before: