One of the major differences between software and hardware is the concept of a clock. It defines the rhythm the sequential elements update inside the chip. Note that in complex System-On-Chips (SoC) there are many clock frequencies that distribute to parts of the silicon. In this post, we will take a basic look at a clock. At the bottom of this post, you will find links to the previous posts. The “ASIC FUNDAMENTALS” series of blog posts starts with “synchronous design” and the rest follows chronologically after that first post.
External or Internal?
A synchronous design requires clock frequencies supplied to it. Now, in a mixed-signal design, they use older VLSI technology nodes. For example, today it is, for example, the 40nm process technology. While the groundbreaking Systems-On-Chip (SoC) use the 7nm and soon 5nm (planned production in 2021) nodes. And the older nodes have lower maximum frequencies. The digital part of the chip needs a rather slow clock. Since the logic is not that big, a few hundred thousands of gates maximum, one system clock suffices. Thisis important because it is common to have an on-chip oscillator in those designs. It is an analog macro that needs trimming. Essentially, the clock has a variation in frequency over all silicon devices that come out of the "fab” (manufacturing facility). Therefor, the oscillator has a tuning capability for the correct frequency on each chip. We store this trimming value permanently in One Time Programmable (OTP) on-chip memory. Hence, this is a major difference with digital ASICs in the latest technology. There we need much higher frequencies to get the maximum performance for the technology. Whenever we combine a large design and a high frequency clock, we need to partition the design. One large system clock domain is impossible. We explain that when we talk about the clock related back-end work. If we use high-speed communication protocols, then multiple different clocks need to go into those IP blocks. Examples of high-speed protocols are: PCI express (PCIe), USB and Gigabit Ethernet (GbE). Most protocols come in several versions. And protocols like USB are backward compatible, even with the first version released in 1996. Isn’t that amazing? (friendly jab at our colleagues of the SW team) Eat that software engineers, backward compatibility for over two decades!!!
Clocks and more clocks?
Anyway, to cut a lengthy story short, essentially an ASIC has one or more external reference clocks. Essentially, we need to keep in mind that the wiring on a development board (PCB), the chip socket (if any) and the path from the pin to the internal logic of the chip deteriorates any signal. Phase noise and jitter are important parameters for the stability of a signal. Specifically, phase noise is the instability of a frequency in the frequency domain, while jitter is the fluctuation of the signal in the time domain. Therefor we use rather low frequencies as an external reference clock. And multiply the clock in the chip. Internally a "Phase-Locked Loop“ or PLL is basically an analog design (macro) that turns a slow clock into a fast clock. For example, for USB version 2, we need 480 MHz. The easiest way to get such a PLL is to license it as IP from a supplier. An input frequency of 20 MHz can turn into a 480 MHz with a clock multiplier by a factor 24.
The choices in clocks and their source, external or internal, are important for the chip. External components contribute to the power consumption of the product. They also add to the Bill Of Materials, or BOM cost. Internal PLL’s come with a cost as well since they are IP or designed by the analog team. Hence, the product manager and the chip architect propose a technical solution that fits the business case.
What did we learn in this post?
In the mixed-signal world, we generally use older technologies with lower clock frequency requirements for the digital part. On-chip oscillators are quite common, but they require tuning to the right frequency. On the other hand, digital ASICs use external oscillator clocks. External clocks are slower frequencies that do not degrade much over the path they follow to reach the inside of the chip. Hence, they can clock the sequential elements directly or we can use it as a source clock for a clock multiplier, a PLL. The next step is a look at the implications for the back-end team. The engineers that do the actual place and route of the design need to take special care of clocks too.
Prerequisites to this post: