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The architect of the chip needs to foresee the future. Therefor, it is important to understand the clock and reset network. Big synchronous clock domains get in trouble during the back-end clock tree synthesis. Avoiding problems like that is the value of the architect. Based on the requirements, the architect writes a specification and draws a top-level block diagram. A preliminary floor-plan is always helpful to visualize the chip layout. Putting two functional serial interfaces together in one part of the design isn’t great if the IO for one interface isn’t close to the other one. With this example in mind, functional grouping is potentially making the layout team’s work very difficult. Functional grouping should respect the physical locations of the chip IO pins.

In HDL designs, verification engineers use interfaces to bind data generators and scoreboards to certain units inside the design. For functional coverage, one can add SVA (assertions) and coverage groups to certain interfaces. But after synthesis, those HDL abstractions translate into a real technology specific circuit (netlist). And synthesis needs to preserve those interfaces for verification. “Gate-level” simulations run a subset of the same test cases that verification runs on the original RTL code. In the nineties, we knew that synthesis does optimization of the design. Boolean algebra simplifications, merging duplicate logic and other interesting area reduction techniques that EDA tools are good at. But it requires flattening the artificial boundaries that the block diagram imposes on the chip. Of course, there are always exceptions to those rules. But our rule of thumb was to verify the design as a black box, exactly the same way as we would verify the silicon. In fact, a good system architect will allow no “cheating” by peeking and poking in the design. The same verification regression runs on RTL, on the prototype (usually FPGA) and on the silicon. Of course, there is some minor difference related to messaging and debug output on your terminal screen. Still, essentially the same code runs without knowing if it is simulation, prototype or silicon that it verifies. Portability is key to keep the effort to the minimum. This means without reworking the code for each target.

So, in our block diagram, our clock and reset modules are the most important. I mentioned the clock tree before. Every clock domain has its associated reset. You can’t use a reset from another clock domain. In ASIC design, register enter the reset state asynchronously. This means immediately when the reset activates, the registers reset. If you consider a Finite State Machine (FSM) with a state that is over one bit wide. The reset exit must be synchronous to the clock of those state registers. If this was asynchronous as well, then the state could exit reset for one register just before the active clock edge, and for the other state registers, after the active clock edge. One or more state bits might already catch the next state value, while others would have their reset value. After reset, one would not be certain of the state of the FSM. Therefor, we exit the reset state on the active edge of the clock. And therefor, the reset signal is always valid only for that clock domain.

On top of the association, every clock and reset need a bypass for Design For Test (DFT). DFT creates the extra logic the chip has on top of purely functional logic. Essentially, this extra logic is used to verify the chip has no manufacturing defects. Minor defects like shorts or opens can compromise the chips function in the field. Therefor, specific test patterns make sure most they catch common manufacturing defects. Now, DFT requires that we use multiplexers on all functional clocks and resets. The best way to do this is to have clocks and resets in one place. Of course, if the chip is big, each subsection of the chip will have one or more clock and reset modules. Still, the idea is to keep clocks and resets apart in a separate unit.

Once we go further down the power saving path, we can disable certain clocks in the design. Dynamic power consumption is proportional to the frequency of the clock. Hence, we gate off the part of the system that is not useful for a certain application. Obviously this applies to applications where a part of the chip is not active. Static gating isn’t always possible. Sometimes, dynamic clock gating is possible. For example, an internal bus that enables the clock only during a transaction. Only caveat is that we cannot create glitches on the clock by static or dynamic gating clocks on and off. A spurious clock pulse potentially violates the maximum frequency or duty cycle requirements. It brings the logic connected to that clock in an unknown state. Something we avoid at all costs. Therefor, the clock-reset module is the only place where we have clock and reset manipulation. Whenever we need to multiplex or gate clocks, we use technology specific cells to create a glitch free signal. By design, those modules are safe.

Safety and reducing risk is the challenge for all semiconductor engineers. That is where we add value.