One of the major differences between software and hardware is the concept of a clock. It defines the rhythm the sequential elements update inside the chip. Note that in complex System-On-Chips (SoC) there are many clock frequencies that distribute to parts of the silicon. In this post, we will take a basic look at a clock. At the bottom of this post, you will find links to the previous posts. The “ASIC FUNDAMENTALS” series of blog posts starts with “synchronous design” and the rest follows chronologically after that first post.
What is a clock?
In synchronous design, the key concept is a rhythm of updating in the design. This we call a clock frequency or clock period. Important, the clock period is the reciprocal of the clock frequency. A clock with a frequency of 1GHz has a clock period of 1ns.
In the digital design world, we work with ones and zeros. We like to keep things simple. So, a clock is a square wave with a high period (digital ‘1’) and a low period (digital ‘0’). The ratio between the time the clock is high versus the total period of the clock is the “duty cycle” of the clock. For example, a duty cycle of 40% means the clock is high 40% of the clock period and low for the remaining 60%. This is an important ratio to remember.
How does a clock influence the power consumption?
If we consider the performance of an ASIC, a higher clock frequency (the same as a smaller clock period) is better for performance. Every VLSI technology node has so-called cell libraries that the foundry delivers. The foundry is the company that manufactures your chip. Depending on your requirements, they have three flavors. And they are: speed (clock frequency), area (mm2 = cost) and power consumption. However, there is one caveat. There is always a trade-off between those three. If you want a smaller area, you need to relax on one factor. Maybe even on both of the other two factors.
The synthesis tool translates our HDL design in a circuit of connected cells. An experienced synthesis engineer has three constraints for the tool to influence the output of the synthesis tool. Heck, there are even levels of effort for those constraints. But simplified, the user tells the tool the priority and importance of the clock frequency, the area consumed by the design and the power consumption of the design. The latter has a static and a dynamic component. The more switching activity of a transistor (zero to one, one to zero) in a circuit, the higher the dynamic consumption. Since the clock is also switching with a certain frequency, reducing the frequency reduces the power requirement. But the reason we need power simulations is that the synthesis tool knows nothing about the application of the chip. Special measures like clock gating, and power islands are very specific. They need a simulation to extract a realistic number of toggling inside the chip. To conclude our power related writings, static consumption is more accurate with synthesis tools since it requires no activity. Static power has two main contributors, leakage power of the transistors and standby power from the DC supply to ground (GND).
What did we learn in this post?
A clock is a square wave, with parameters associated to it. If we want better performance of the circuit, there is always a trade-off between performance, area and power.
Two other posts precede this one: