ASIC FUNDAMENTALS: how do we design an ASIC?

One of the major differences between software and hardware is the concept of a clock. It defines the rhythm the sequential elements update inside the chip. In complex System-On-Chips (SoC) there are many clock frequencies that distribute to parts of the silicon. And since it is a basic thing for any digital design, let’s look at the ASIC first. So, let’s define what an ASIC is and describe how we design it.

What is an ASIC?

An Application Specific Integrated Circuit or ASIC is like a clean slate. We are talking about the actual silicon of a chip. Basically, it is a silicon substrate with millions, even billions of transistors. And we, the designers, decide the way we connect those transistors to each other. This wiring defines the function of our circuit. Noteworthy is that digital designers work with boolean logic. Hence, we don’t use the transistors. Nope, we use so-called gates (or cells). They combine a number of transistors together so we can use the boolean equations from our micro-electronics education.

How do we design an ASIC?

Boolean algebra uses a simplified version of variables. We call them truth values, they are “true” or “false”. That is what I love about digital design, the simplicity. The “Keep It Simple and Stupid” (the KISS principle) is the basis for everything I do. Avid readers of my writings know this. Specifically in electronics, “true” and “false” become “1” and “0”, a high voltage and a low voltage. Noteworthy is that boolean algebra has three primary operations. They are: AND, OR and NOT. And every complex boolean equation is essentially a combination of those basic functions.

As we all know, digital designers use a “Hardware Description Language” (HDL) to describe our design. The emphasis is on “DESCRIBE” because the languages we call HDLs have a software syntax (”if then else”, “case”, …) but they are NOT software at all. Why? Well, software code (example C/C++) abstracts the underlying processor Instruction Set Architecture. A tool, the compiler, translates the code into instructions that the specific target processor supports. Hence the code can run on processors that have a different ISA. Likewise, in digital design our description of the hardware abstracts the underlying technology. Different foundries (manufacturers of chips) and different technology nodes (5nm, 7nm, 14nm, …) have their specific libraries of cells.
We use a very expensive tool called a synthesis tool to translate this description into a circuit that wires up the cells of our library of choice. The output is an HDL file we call a "Netlist”. Note that this "Netlist” is no longer technology agnostic. It contains the technology specific boolean gates, sequential elements, and nets to connect them all. As discussed in the previous post on my blog, “synchronous design” simplifies the way we design and verify. Similar, the HDL abstraction makes us less dependent on our target technology. In the actual world, we sometimes have to add specific technology cells to our HDL designs. And that makes our code less portable.

What did we learn in this post?

We explained that an ASIC is a chip that contains gates for digital design. And gates allow us to implement boolean algebra. Wiring up those gates implements our digital functionality on the chip. And the way we describe the functionality, as agnostic from the underlying technology as we can, is by writing HDL code. Most noteworthy is the importance of HDL code: it looks like a software syntax but it is NOT software, it describes hardware.

In the next post we are going to answer the question: What is a clock?

Comments (1)


Thomas Dietert

20-06-2021 02:58 PM WEST

Great concise overview of the ASIC design flow! My one qualm is the statement that HDLs are not software, but I think that issue of semantics is outside the scope of this post or comment section. Would love to see a short post on High Level Synthesis (HLS)!

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