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What is the career path for a verification engineer?

The only question right now is, what is your goal as a (verification) engineer? Goal thinkers have a specific goal they want to achieve. A goal could be a salary of x dollar or euro. A different goal, for example, is verification lead or verification architect. Something like that. I started with ASIC verification a few decades back. And I was a goal thinker...

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Lean ASIC design: how to keep the NRE low

Companies complain often about the exploding costs of ASIC projects. Often they don’t realise their shallow cost-saving measures actually cause the entire budget to go off the rails. Especially the frugality in hiring single skilled engineers creates the situation we all know from playing Monopoly. Go back to START, do not pass Go, do not collect $$$. The bi...

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ASIC verification series: both sides of the story

I’m still on both sides of the coin, after over two decades of ASIC design. Hiring and being hired. And both are not always pleasant experiences. Hiring is hard, getting a role is hard as well. We are all individuals, and individuals have an ego. Sometimes it is just the use of a particular word. Or an opinion that triggers the ego to roar its ugly head. Esp...

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Bitcoin ASIC miner startup MVP

Bitcoin ASIC miner MVP A friend of mine is working on a Minimum Viable Product for a BTC miner. Today’s bottleneck is Bitmain not selling enough miners to keep up with demand. In the short term, an FPGA MVP board proves the targeted performance. In parallel, the ASIC team prepares a tape-out. Basically, a realistic timeline is 3 to 6 months to tape-out. Th...

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My recommend reading list

I always enjoyed writing, but my current journey started in September 2017 with writing on Quora. Credit where credit is due, I unexpectedly received a message in 2018 that I got a top writer badge on Quora. And looking back at my initial writing, perhaps only related to the niche topics VLSI and semiconductors, that was a surprise. So surprising, that it ke...

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ASIC Fundamentals: The Architect

Looking to the current ASIC design projects, we see a discrepancy. The EDA companies push a narrative that all is well as long as you buy their tool chain. That is what I call the Disney version of reality. Real projects today rarely start with a signed off specification. Modeling the chip for feasibility is rare today. Without the proper validation and spec...

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ASIC fundamentals: The clock reset module

The architect of the chip needs to foresee the future. Therefor, it is important to understand the clock and reset network. Big synchronous clock domains get in trouble during the back-end clock tree synthesis. Avoiding problems like that is the value of the architect. Based on the requirements, the architect writes a specification and draws a top-level bloc...

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ASIC startup: hardware is hard (Google CEO Pichai)

Take it from Sundar Pichai, CEO of Google. Hardware is hard. And Google is a software giant that designs its own chips. Other trillion dollar companies, Amazon, Apple and Microsoft have hardware design teams too. Even Facebook has ASIC designers on the payroll in 2020. General purpose processing started the boom in hardware in the 20th century. Then multi-pu...

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ASIC FUNDAMENTALS: how do ASIC clocks fit into an FPGA?

One of the major differences between software and hardware is the concept of a clock. It defines the rhythm the sequential elements update inside the chip. Note that in complex System-On-Chips (SoC) there are many clock frequencies that distribute to parts of the silicon. In this post, we will take a basic look at a clock. At the bottom of this post, you wil...

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ASIC FUNDAMENTALS: how does the back-end engineer deal with clocks?

One of the major differences between software and hardware is the concept of a clock. It defines the rhythm the sequential elements update inside the chip. Note that in complex System-On-Chips (SoC) there are many clock frequencies that distribute to parts of the silicon. In this post, we will take a basic look at a clock. At the bottom of this post, you w...

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ASIC FUNDAMENTALS: how do synthesis and STA deal with a clock?

One of the major differences between software and hardware is the concept of a clock. It defines the rhythm the sequential elements update inside the chip. Note that in complex System-On-Chips (SoC) there are many clock frequencies that distribute to parts of the silicon. In this post, we will take a basic look at a clock. At the bottom of this post, you w...

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ASIC FUNDAMENTALS: how do we deal with multiple clocks?

One of the major differences between software and hardware is the concept of a clock . It defines the rhythm the sequential elements update inside the chip. Note that in complex System-On-Chips (SoC) there are many clock frequencies that distribute to parts of the silicon. In this post, we will take a basic look at a clock. At the bottom of this post, you w...

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ASIC FUNDAMENTALS: do we use an internal or external clock?

One of the major differences between software and hardware is the concept of a clock . It defines the rhythm the sequential elements update inside the chip. Note that in complex System-On-Chips (SoC) there are many clock frequencies that distribute to parts of the silicon. In this post, we will take a basic look at a clock. At the bottom of this post, you w...

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ASIC FUNDAMENTALS: what are the important parameters of a clock?

One of the major differences between software and hardware is the concept of a clock . It defines the rhythm the sequential elements update inside the chip. Note that in complex System-On-Chips (SoC) there are many clock frequencies that distribute to parts of the silicon. In this post, we will take a basic look at a clock. At the bottom of this post, you w...

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ASIC FUNDAMENTALS: what is a clock?

One of the major differences between software and hardware is the concept of a clock. It defines the rhythm the sequential elements update inside the chip. Note that in complex System-On-Chips (SoC) there are many clock frequencies that distribute to parts of the silicon. In this post, we will take a basic look at a clock. At the bottom of this post, you wil...

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ASIC FUNDAMENTALS: how do we design an ASIC?

One of the major differences between software and hardware is the concept of a clock. It defines the rhythm the sequential elements update inside the chip. In complex System-On-Chips (SoC) there are many clock frequencies that distribute to parts of the silicon. And since it is a basic thing for any digital design, let’s look at the ASIC first. So, let’s d...

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What drives the main cost of an ASIC?

The main cost of an ASIC, an Application Specific IC is related to the complexity. Basically, the silicon we start with is a clean slate. Imagine a circular surface, called a wafer, with billions of transistors. With a special technique, we will interconnect all transistors via metal layers on top of the silicon. Then the wafer is cut in squares, called dies...

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ASIC FUNDAMENTALS: what is synchronous design?

One of the major differences between software and hardware is the concept of a clock. In essence, it defines the rhythm of updating the sequential elements in the chip. And we call it synchronous design. In big complex system-on-chips there are many different clock frequencies that are distributed to parts of the Integrated circuit (IC). And digital design...

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Lean Mean Verification Machine: Appetite For Destruction (*)

We all have this inner urge to destroy, isn’t it? Not by default. We are good people, right? It definitely needs a trigger. Some alcohol could do the trick. Or after a bad night of sleep combined with some major setback. Or Saturn lines up with the moon while Venus plays online chess with Mars. This primal instinct is important for the verification engineer....

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Careers in VLSI: who gets the best salary?

Analog, mixed-signal or digital design engineer? None of them get paid what they are worth. Let’s be clear about that. And this is good nor bad, it is the way it is. The stoic does not attach an opinion to an observation. Furthermore the skills for hardware engineers are quite specific and hard to find. Especially if we compare ourselves versus our nemesis...

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