What is an ASIC designer?
A digital VLSI engineer starts his or her career usually as a verification resource. Verification exposes you to the HDL language. Hardware description languages like VHDL and verilog. The difference in syntax between behavioural code and RTL implementations is important. Because, the designation "RTL" (register transfer level) means that the code can be translated by a synthesis tool into logic. That means digital logic, gates and flipflops. Behavioural code is not necessarily synthesizable. We use it for testbenches for example. So, it doesn’t need to be synthesizable. Hence a verification engineer uses the full syntax of the language. The design engineer needs to restrict himself or herself to the synthesizable subset of the language.
What is an ASIC verification engineer?
The verification engineer writes testbenches and runs simulations. A designer needs more experince with HDL’s, he understands the subset of the HDL that is synthesizable and knows the relationship between his code and the hardware. He can already foresee timing issues by coding accordingly, for example pipeline arithmetic algotihms. A designer needs a text editor, scripting experience, simulation experience and digital logic knowledge (including synthesis). A verification engineer needs a text editor, some scritping experience and a simulator.
CONCLUSION
Often misunderstood, big companies have put every front-end resource in a category. They invented the ASIC design engineer, the ASIC verification engineer (aka UVM engineer), the synthesis and STA engineer, the DFT engineer, the gatelevel verification engineer, the FPGA prototype engineer, ... In contrast, small companies usually rely on front-end designers that can do most if not all those tasks. The underlying reasoning is that they want to hire low cost employees and subcontractors. Engineers that have not worked for 15 years and have been doing all tasks. They are expensive if you hire them solely to do verification. Or DFT, or STA, ... By changing the profile, they have effectively cut the front-end into separate fields severing the connection between them. What started as a cost cutting effort has actually achieved the opposite. ASIC budgets exploded to a few hundred million for a 7nm tape-out of a complex System-On-Chip. The reason is simple. If you don't know how to properly verify on the appropriate level. And if you don't know how to write RTL code to make sure it passes STA, DFT and synthesis requirements later on. Then you create an enormous spaghetti of loops from DFT, STA and synthesis to the designers of the units. Bugs filed against RTL for DFT, STA and synthesis violations can happen. But today is the rule instead of the exception. Moreover, front-end engineers that can do all tasks, have a difficult time getting past recruiters. They get their instructions from their customer and look for exact keyword matches. They are unable to assess qualifications because they rely on a set of keywords. Whenever one gets past a recruiter, by accident one might say, the project leader or manager has the same narrow focus. They can assess qualifications but have always worked in a situation where it is more cost effective to have a person that has done only UVM and no design, synthesis, STA and DFT. They are trained to think in partitioned tasks too. They don't care that the project is extremely stressful due to everything going in circles all the time. It makes them needed (so much management to do). They need more resources because they are falling behind. Remember the time we thought engineers are trained in logic and in finding the problems and fixing them? Part of the education otherwise no graduation. Well, today you can razor sharp point to major issues in the front-end design cycle. Costing millions of dollars. Hence, the pencil pushers come in to make it all a process. Every step is defined after weeks and months of meetings and writing documents. Milestones and sign-off with signatures of all stakeholders after a formal review. Quality assurance engineers come in. And auditors, external and expensive. And all it accomplishes is that the project responsables are trying to pass milestones for the sake of the milestone. It doesn't improve the quality of the work or efficiency. It doesn't solve the lack of experience, the lack of a sound methodology, the lack of care about the failure or success of a chip. In my book those engineers should hand in their degree. They don't deserve to be called engineers. They are drones, getting money to eat and do things they like to do outside their field. They are NOT committed, they are NOT out-of-the-box thinkers, they are NOT even in-the-box thinkers, they are NOT efficient, they simply learned to not care and keep their piehole shut.
I apologise for the dramatic and outdated wording (quote from 200 years ago) but this is kind of describing what I want to explain:
“The only thing necessary for the triumph of evil is for good men to do nothing.”
Edmund Burke (in a letter addressed to Thomas Mercer).